Gallium arsenide is a semiconductor material that is generally used for high frequency applications due to the high carrier mobility in comparison with silicon devices. The manufacturing process associated with GaAs is similar to that of Si, but the physics associated with each semiconductor material makes them suitable for different applications.
The advantages in speed and high frequency performance of GaAs are slightly offset by the process limitations of GaAs as opposed to Si. GaAs wafers are only four inches in diameter (compared to twelve for Si). This limits the number of devices produced per wafer, and thus the final monetary value of each wafer. The wafer size limit is due to the strength of the material. If you’d like to learn more, visit the section about crystal growth.
GaAs is well suited for RF and microwave devices due to its speed. The RF devices consist mainly of cellular phones, beepers and the like, while the microwave devices are usually built for military contracts.
GaAs devices generally originate in one of two ways. RF devices that are used in commercial applications are the result of design engineers improving upon past devices or addressing a marketable issue. Microwave devices are usually built to meet a military specification. The design process described below is typical for RF devices, and notes will be added where the process differs for microwave applications.
Once a target spec has been generated by a design engineer (or handed down from the military in the case of microwave devices), a group of engineers and marketing specialists will meet to discuss the specific concept. The feasibility of the proposed device is evaluated, and the proposed spec is adjusted as necessary. The design engineers then develop the initial circuit to meet the required specs.
After the circuit is designed, the circuit is compared to a list of design rules to determine if the process engineers can build the components that the circuit design engineers have requested. The circuit design is limited by the values of resistors, capacitors, and inductors that can be manufactured on the semiconductor wafer, and also by the properties of the MESFETS that can be built. The process engineers and the design engineers work together to produce an acceptable layout.
After the layout is finalized, photo-masks are ordered. The photo-masks are clear quartz plates with opaque chrome images. The masks are used in the positive and negative lithographic techniques to transfer the desired circuit design to the GaAs wafers.
GaAs is a III-V semiconductor. This means that the crystal is composed of atoms from groups III and V of the periodic table. The atoms are arranged in a lattice in a manner similar to that of diamond or silicon. This variant of the diamond structure is known as 'zinc-blende'. Each atom in the lattice is bonded to four other atoms of the opposite type. GaAs is doped by exchanging a different atom for one of the Ga or As atoms. A group II element on a group III site makes the material p-type. A group VI element on a group V site makes the material n-type. Silicon is an amphoteric dopant in GaAs. If it is placed in a Ga site the material is n-type and if it is placed in an As site the material is p-type.
The GaAs crystal structure |
The physical characteristics of GaAs make it the natural choice for high speed devices. The mobility of electrons for GaAs is 8500 cm2/V-s, as opposed to 3900 cm2/V-s for Si, while the mobility of holes in each material is roughly the same. The band gap of GaAs is a direct band gap of 1.42eV, and a high electric field can be applied along the (100) direction due to the high peak before the secondary valley in this crystallographic direction. The band diagram of Si illustrates that less energy is needed for an electron to jump into a secondary valley, and large voltages cannot be applied.
Layout engineers take advantage of the high peak in the (100) direction to build the fastest devices possible. By aligning the drain and source of the MESFETs along the (100) direction, a large VDS can be applied. The large value of VDS means that the electric field between the drain and source is greater, and thus the force on the carriers is greater. The maximum field that can be applied along the (100) direction is approximately 3kV/cm.
The designer of a microelectronic circuit has all of the same problems as other designers and then some. A micro designer still has a goal that needs to be met within a set of specifications, but the microelectronic designer is also limited by the devices that can be made on the semiconductor wafer. When so much money is put into the creation and preparation of GaAs and similar materials, it is important to get the most from the given space. Space as small as a few microns can mean a lot of money when put in the context of several thousand chips. The major space hogs of microelectronic devices are its components. Component choice is crucial and it may be better to attach large components externally to save space. Another consideration is metalization thickness compared to power loss. If too much power is flowing through too thin of a line, the line may snap like a fuse. Some other things that the micro electronic designer should also consider are the issues of cross talk and noise amplification. If two different signals are running too close to each other they may effect each other by an effect known as cross talk. When noise is introduced close to an amplification stage, the noise will be amplified along with the signal. The layout engineer works closely with the design engineer to design the optimum circuit for production.
The design engineer specifies the values of components, and the general characteristics of the transistors to be used. To the design engineer, the schematics look the same for IC or discrete circuits, but the component values are smaller in IC designs. Similarly, a MESFET is just another symbol on the schematic, but to a layout engineer its an entirely different design problem. A typical GaAs RF circuit is shown Below.
A typical RF circuit (Source:Shur) |
Three passive components, in addition to the active devices (diodes and transistors) are also required to be created "on-chip". There are resistors, capacitors, and inductors.
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Resistors can be valued up to around 1M ohm, but the larger the resistor is, the more chip space it requires. Some devices may require resistors that are small enough to make on a wafer, but would make the chip more affordable or smaller by connecting them externally. |
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Capacitors should at or below the 20x10-12 Farad range. Like inductors the amount of space needed for large capacitors dictates an external connection for large capacitors. |
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Inductors should be on the order of 4x10-9 Henrys or smaller. Because of the way they are created on GaAs, inductors of any larger value should be attached externally. |
Resistors are made by connecting to pieces of metalization with a section of the n type GaAs, and using the materials natural resistivity. The value of the resistor is a function of its length, width, and resistivity of the GaAs.
Capacitors are made by separating two layers of metalization with a dielectric material. The capacitance are a function of the dielectric and the areas of the metalization plates.
Inductors are made by looping the metalization around itself. The inductance is a function of the number of loops and the distance between the loops. To connect to the inner end of the inductor one must either place a layer of dielectric between the inductor and the crossover, or the crossover can be wire bound to separate it from the inductor.
A MESFET is a Metal-Semiconductor Field-Effect Transistor. MESFETS are the basis of all the RFIC and MMIC devices built at GaAs TEK. A cross-sectional view of a typical MESFET is shown below. MESFETs are made by building layers on top of each other, and doping the semiconductor material to a profile similar to that shown below.
These transistors work on the same principle as other field effect transistors, but the difference between MESFETs and other field effect transistors is that MESFETs have no oxide layer between the gate and the channel of the device. The design relies on the Schottky barrier, generated when the metallization comes in contact with the semiconductor material, to minimize the leakage current through the gate.
The first step in building GaAs MESFETs is to ion implant a deep p-type layer below the surface of the substrate. This p-type layer is generally a group 2 element such as magnesium. The purpose of the deep p-type layer is to cause a sharp transition from n-type material beneath the channel of the FET. This makes the device less susceptible to noise and easier to control. Silicon is then ion implanted just below the surface to make the n-type channel of the FET. Silicon is an amphoteric material, which means that it can be used to create either n or p-type layers depending on the temperature at implantation. GaAs TEK implants at room temperature, so the Si becomes a donor.
It is important to note that GaAsTEK uses only ion implantation and no diffusion. This is because the high temperatures necessary for diffusion would cause the arsenic to evaporate readily. It is for this same reason that they prefer to use sputtering instead of evaporation. The heat associated with evaporation or diffusion also make it necessary to keep close tabs on a thermal budget. The cooler (room temperature) processes are cheaper and simpler.
The next step in the process is to form the gate of the transistor by depositing TiWNi by sputtering. A thin layer of the channel near the surface of the device is doped heavily with donors. This heavy n-type doping makes the contacts at the drain and source more ohmic. SiON is then deposited over the transistor, and a positive lithographic process is used to deposit ohmic metallization on the drain and source.
The layout drawing of the circuit is a series of layers that create the devices that were specified by the circuit designer. Every layer in the layout drawing corresponds to one mask in the processing of the GaAs wafer. A typical RF device will have ten to thirteen layers, but a complex microwave circuit may have as many as 20. The final layout drawing at GaAs TEK is sent to Photronics, a photo-mask company, and the masks are generated from the layout files. It is very important that there are no errors in the layout drawings because each mask (corresponding to one layer in the process) costs between five hundred and one thousand dollars. A layout error can be a very costly mistake, so care is taken to review the final layout thoroghly.
The layout engineer has the final word on whether or not a circuit can be fabricated. It is the responsibility of the layout engineer to advise the circuit designer about what components are not able to fit in an IC package, and to convert the circuit that has been designed into a series of layers that build the devices. The layout engineer uses a library of information that has been compiled about transistor performance to meet the needs of the circuit designer as closely as possible. The MESFETs that are used are a result of past fabrication and testing, and sometimes the result of new theories about performance. ITT is currently experimenting with a new gate formation to enhance device performance. This type of improvement incorporates past experience and new ideas.
The photo-masks used for semiconductor manufacturing processes are similar to the negatives created when you use a camera. The two types of lithographic processes (positive and negative) each require a different kind of mask. Positive lithographic processes etch away the material that is not hidden by the opaque area of the mask. Negative lithography etches away the areas beneath the opaque portion of the mask.
The masks used at GaAs TEK are reduced by a factor of five when they are projected onto the wafer during the lithography processes.The pattern on the mask is stepped over the entire wafer surface, and the desired effects of the layer are transferred to the wafer. The image on the mask, or reticle, is composed of several die. The die are the circuits that are being transferred to the wafer. In the initial run of a circuit, each of the die may be a different variation of a circuit. This allows the design and layout engineers the opportunity to try several ideas in one processing run.
The picture below illustrates how a mask transfers an image to the wafer.
