Crystal Growth and Wafer Fabrication
After Mitsubishi, Dowa and ITTGasTek
The production of Gallium Arsenide (GaAs) semiconductors begins with crystal growth.
There are many ways of growing GaAs single crystals, the most popular being the Liquid
Encapsulated Czochralski (LEC) method. In the LEC method, there is a crucible loaded with
gallium, arsenic and boric oxide. This crucible is placed in a pressure vessel. This
vessel is evacuated, filled with argon and then pressurized. The temperature is raised
within the vessel causing the gallium and arsenic elements to react and form gallium
arsenide. As the temperature increases, the resulting gallium arsenide melts, as does the
boric oxide. A seed is then dipped into the melt and slowly retracted creating a
crystalline block that is often called an ingot or boule. After the ingot is completely
retracted and cooled, individual wafers are sawed from the ingot. The wafers are then
lapped, polished and ready for inspection. The completed wafers are inspected, packaged
and finally shipped to a consumer. The consumer will put each wafer through various
processes such as lithography, circuit design/mask creation, ion implantation and
metallization in order to make the wafers into semiconductor devices. However, the process
of creating a GaAs semiconductor can not occur without proper crystal growth and wafer
fabrication, which begins with the Liquid Encapsulated Czochralski growth technique.
Necking and Cone Angle
Necking is the process of reducing the seed diameter while pulling the seed from the
melt. Dislocations are introduced to the crystal from the seed if the seed initially has
dislocations. The dislocations can be transmitted from the seed to the crystal. This is
the reason for necking the seed. When the seed is necked, the amount of dislocations that
migrate to the crystal is reduced. Using a dislocation-free seed does not always prevent
dislocations from forming in the crystal. However growing a cone after the neck reduces
the amount of dislocations formed in the crystal. Figure A shows that etch pit density
(EPD) decreases as cone angle increases, but only up to about 25 degrees. Beyond 25
degrees, the EPD stays approximately the same. As the cone is pulled from the melt, the
dislocations start to increase, reach a maximum, and then decrease before reaching the
maximum crystal diameter. With no cone, these dislocations would form in the body of the
crystal and ruin the ingot. For cones with steep angles, the most dislocations occurr near
the center of the cone. [Kirkpatrick]
Neck and Cone of the Ingot
Source:Fullman Company
Source:Park Scientific Instruments
Twins
There are some defects that occur when growing a crystal. The major defects are twins
and dislocations. Twins can change the crystallographic orientation of the material as
well as create large grain boundaries. Twinning can also lead polycrystallinity.
Therefore, in order to achieve single-crystal wafers suitable for device fabrication,
twinning must be eliminated. As it turns out, controlling the stoichiometry of the melt
during the LEC growth can prevent twin formation in semi-insulating <100> GaAs crystals.
Experiments show that using an undoped arsenic-rich melt, the probability of twinning
decreased significantly thus allowing large diameter single crystals to be grown. Twinning
is not correlated to other growth parameters [Kirkpatrick]. For
gallium-rich melts, the probability for twinning increased significantly.
Dislocations and Etch Pit Density
Dislocations are defects in crystals that produce unsaturated bonds. Dislocations can
cause all sorts of problems in wafer and device manufacturing. The main cause of
dislocations is due to stress in the crystal caused by thermal gradients during crystal
growth. Dislocation density can be quantified by counting etched pits created by etching
wafer with potassium hydroxide. There is a direct relation between etch pit density (EPD)
and dislocation density. These terms are used interchangeably [Williams]. There are
many parameters that affect the amount of dislocations in the crystal including, cone
angle and seed quality, boric oxide thickness, diameter control and melt stoichiometry.
While pulling the seed, creating a neck and increasing the cone angle can reduce the
amount of dislocations in the crystal.
Figure A
Source:Kirkpatrick
Experimental results also show that as the boric oxide layer is made thicker, the amount
of dislocations decreases due to better heat flux and reduced thermal gradients. Diameter
control also affects dislocation density. Good diameter control leads to lower dislocation
densities. This result is much less pronounced than cone angle, seed quality and oxide
thickness results. Melt stoichiometry also reduced the dislocation density when using an
arsenic rich melt. Experimental results suggest using a As-rich melt composition of 0.505
to 0.535 for optimal reduction of dislocations. But like diameter control, the affects of
melt stoichiometry on the dislocation density was less pronounced that of the others [Kirkpatrick].
After M/A-COM Inc.
Heat distribution during crystal growth
Heat Flux and Thermal Gradients
Heat flux plays a critical role during crystal growth. In order to grow a single
crystal, the melt-solid interface must be maintained at a constant temperature of 1511 K,
just below the melting point of GaAs. This allows for the melt to solidify onto the
crystal. Since heat flux and isotherms are perpendicular to each other, analyzing the
interface shape in figure A shows that significant heat flows from the crystal to the
boric oxide layer. This can lead to polycrystallinity, hence reducing the heat flux into
the boric oxide will produce a single crystal. Raising the boric oxide temperature close
to the crystal temperature will reduce the heat flow rate from the crystal to the oxide
layer. The resulting interface is seen in figure B, which will produce desirable long
single crystals [Ware].
Figure A
Source:M/A-COM Inc.
Melt/crystal barrier leading to polycrystallinity
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Figure B
Source:M/A-COM Inc.
Ideal melt/crystal barrier in producing single crystals
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Steep temperature gradients are also established in GaAs crystals during LEC growth.
Temperature gradients cause dislocation and can leave strains within the crystal. These
strains can cause cracks in the crystal and render it useless. The strains are avoided by
annealing the crystal before cutting, but dislocations are often still present.
Dislocations decrease as the thermal gradients and heat flux decrease. Reducing thermal
gradients is accomplished by heating the boric oxide layer (as explained above) or
increasing the thickness of that layer. Figure C shows dislocation density (EPD) as a
function of the boric oxide thickness.
Figure C
Source:Kirkpatrick
Dislocations at the front of the crystal drop significantly as the oxide layer
thickness increases, but dislocations at the tail only drop slightly. However, as the
boric oxide layer increases, the control over crystal diameter decreases [Kirkpatrick].
Slicing
After the ingot’s outer surface has been smoothed out and taken off
the lathe, the ingots need to be sliced into wafers. This is done by placing the ingot
horizontally on a holder (Figure C) so that the holder can move the ingot up into the
circular saw. This saw is commonly referred to as an "ID Saw" because its
cutting edge of the blade is on the inside (Figure D). The "ID Saw" is notorious
for producing a more precise cut as well as a wafer that is flatter (Fullman Company). The
saws used to cut the ingot into wafers have a diamond blade or a blade made with a
composite material that has diamonds in it (Williams). These saws
cut wafers with a thickness of 625 micron. The wafers are thinned down later to
approximately 100 micron. The wafers are sliced at 625 micron so that they aren’t as
brittle as the 100 micron wafers when handling them (Figure E).
Figure C
Source:Mitsubishi
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Figure D
Source:Fullman Company
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Figure E
Source:ITT GaAsTek
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Source:Fullman Company
Polishing
After the flats have been ground into the ingot and the wafers have been sliced, the
wafers are lapped. Lapping is often done by applying a slurry of water and grit to the
wafer. The grit is typically constructed of silicon carbide or alumina (Williams). This slurry
helps to remove saw marks and to make the surfaces of the wafer more parallel. After
lapping, the wafers are etched to remove surface damage done to the wafer by the previous
process. Next, the wafers are polished. Polishing involves two or three steps of chemical
processes. The wafers are also buffed with a slurry. Most (Fullman Company)
companies use a polisher that polishes both sides of the wafers simultaneously. Figure F
is a picture of a wafer polishing machine.
Figure F
Source:Speedfam
Inspection
When the wafers have been polished the next step is to inspect them for defects, such
as particles and haze. Figure G (below) is an example of a machine that can perform the
functions that are needed to inspect the wafers for such defects.
If the polished wafers pass inspection, they are packaged and sent off to the customers
(like ITT GaAsTek). When the customer receives the shipment, the wafers are inspected to
insure they meet each company's own standards. All companies check for defects, but also
for brittleness. Since the wafers have to withstand the rest of the IC (Integrated Chip)
manufacturing process, they must be strong. ITT GaAs Tek uses a test in which a machine
places a Teflon ball on the wafer and presses down on the ball with the desired amount of
weight. The Teflon ball keeps the wafer from being scratched. If the wafer handles the
weight and does not crack, then it is passed on to the photolithography process. Most
wafers that ITT GaAsTek obtains can handle up to 30 pounds of weight.
Figure G
Source:Tencor
Copyright © ITT GaAsTEK and Virginia Tech
main/waferfab/Crystala.htm
